This invention relates to a single side, two-step anisotropic etching process for the fabrication of three dimensional devices from silicon, and more particularly, to the use of the this process for fabricating silicon devices having both large recesses and high-tolerance, small recesses, such as for example, the ink flow directing part of a thermal ink jet printhead. A fundamental physical advantage of anisotropic etching in silicon is that the (111) crystal planes etch very slowly while all other crystal planes etch rapidly. Consequently, only rectangles and squares can be generated in (100) silicon material with a high degree of precision. Even with etch masks having only rectangles and squares, the dimensional precision of the etched recesses require that the edges of the mask vias defining the rectangles and squares be aligned with the intersection of the (111) and (100) crystal planes. In the semi-conductor industry, it is common to have silicon devices containing large recesses or through holes in a silicon wafer and relatively shallow high tolerance recess associated with them. For example, an ink jet printhead may be made of a silicon channel plate and a heater plate. Each channel plate has a relatively large ink reservoir etched through the silicon plate so that the open bottom defines an ink inlet and has a set of parallel shallow elongated channel recesses communicating with the reservoir at one end and opened at the other end to form nozzles. The channel recesses require precision geometries with very high tolerances. When the channel plate is aligned and bonded to the heater plate, the large recess becomes the ink reservoir and the shallow elongated channels become the capillary ink conduits between the nozzles and the reservoir, as described more thoroughly in U.S. Pat. No. RE 32,572.
In such printheads, it is frequently desirable to generate a large reservoir which is often etched completely through a 15 to 25 mil thick wafer with small perpendicularly adjacent channels which may be only 1 or 2 mils deep on the same silicon substrate surface. A major difficulty associated with fabrication of such a structure is that the channels and reservoir must be separately etched and then subsequently joined by a variety of methods, such as, for example, the use of a thick film layer on the heater plate that is patterned and etched to form ink flow bypasses. Generally, channel plates are formed by etching a plurality of reservoirs in a (100) silicon wafer first and then accurately aligning the channels to the edge of the reservoir in a second lithographic step followed by etch mask delineation and a second, short anisotropic etch step sufficient to etch the depth of the plurality of sets of associated channels. An advantage of such a process is that control of channel dimension would be very high because the mask defining the channels will be undercut about 1/10th as much as would be the case when the channel and reservoir are delineated simultaneously. This is because the (111) planes have a definite etch rate and the etch time for channels for the two cases is about a factor of 10 different. The problem with such a two-step process is that it is difficult to do a second lithography step on an anisotropically etched wafer due to the large steps and/or etched through holes.
U.S. Pat. No. 4,863,560 to Hawkins, discloses another two-step process for forming three dimensional structures from a silicon substrate by anisotropic etching. In this process, the reservoir and any necessary through holes are formed through a coarse silicon nitride mask as the wafer undergoes a relatively long etching process. Then the nitride mask is stripped to expose a previously patterned high temperature silicon oxide masking layer that is used in a subsequent shorter duration channel etching step. This process avoids the channel width variation problems associated with the previously described single-step process, as the channels are formed during a very short etch duration step. Two problems arise with this process. First, the oxide layer is subject to considerable erosion in some anisotropic etchants, for example, potassium hydroxide. Second, the oxide masking layer is a high temperature thermal oxide process usually carried out at a temperature of about 1,100.degree. C. which can generate high concentration of oxygen precipitant defects in the wafer and disruption of the crystal lattice. Such defects can cause loss of dimensional control, especially of the channels, and result in out of tolerance silicon devices.
Application Ser. No. 07/534,467, entitled "Low Temperature Single Side Multiple Step Etching Process for Fabrication of Small and Large Structure", filed Jun. 7, 1990 to O'Neill, discloses a fabrication process for silicon wafer derived elements, such as channel plates or thermal ink jet printers that include the formation of a final etch pattern in first and second masking layers. The second masking layer is a protective layer to prevent removal of the first layer upon removal of a subsequent third masking layer. Preferably, the second masking layer is an oxide applied under low temperature conditions to lessen the possibility of inducing formation of oxygen precipitates in the wafer. A third masking layer is formed over the final etchant pattern formed by the first and second masking layers. The third masking layer is patterned to form a precursor structure of a large structure contained in the final etchant pattern. After formation of the precursor structure, the third masking layer is removed and the wafer is subjected to a final etching to form the final etched three dimensional structure. The process is useful for forming three dimensional silicon structures, such as channel plates for thermal ink jet printheads.
U.S. Pat. No. 4,875,968 to O'Neill et al., discloses a method of fabricating a thermal ink jet printhead of the type produced by the mating of an anisotropically etched silicon substrate containing ink flow directing recesses with a substrate having heating elements and addressing electrodes thereon. An etch resistant material on the surface of a (100) silicon substrate is patterned to form at least two sets of vias therein having predetermined sizes, shapes and spacing therebetween. The predetermined spacing permits selected complete undercutting by anisotropic etchant within a predetermined etching time period. The patterned silicon substrate is anisotropically etched for the predetermined time period to form at least two sets of separate recesses, each recess being separated from each other by a wall, the surfaces of the walls being (111) crystal planes of the silicon substrate, whereby certain predetermined separately etched recesses are selectively placed into communication with each other by the selective undercutting while the remainder of the undercut walls provides strengthening reinforcement to the printhead, so that larger printheads may be fabricated which are more robust without relinquishing resolution or reducing tolerances. Thus, this patent teaches that certain anisotropic etchants, such as potassium hydroxide, undercuts and etches the etch resistant mask by about 7 micrometers for a full through etch time for a 20 mil thick wafer.
At present, thermal ink jet channel plates are fabricated by two separate potassium hydroxide orientation dependent etching processes or are fabricated by a two-step potassium hydroxide orientation dependent etching process, as disclosed in U.S. Pat. No. 4,863,560. In the latter process, the channel plate reservoir is first etched followed by the etching of the channels. During the second etching step, the masking layer is a thermally grown oxide layer having the disadvantage of being readily etched in the potassium hydroxide etch bath. Thus, the high tolerance, small channel recess must be designed to accommodate not only the undercut of the oxide mask, but the etch removal of the edges of the vias in the mask as well.